Selective deposition of solder ball contacts

ABSTRACT

Some embodiments of the invention include methods of forming solder ball contacts having dimensions of approximately 2.5 microns in diameter for use in C4-type connections. The methods form solder ball contacts using selective deposition of solder on metal contact pads of a device. The metal contact pads have exposed portions at the bottom of through holes. The through holes define the dimensions of the exposed portions of the metal contact pads, and serve to limit the dimensions of the resulting solder contact by limiting the area upon which deposition preferentially occurs. Subsequent reflow of the deposited solder forms a solder ball contact. Various devices, modules, systems and other apparatus utilize such methods of forming solder ball contacts.

RELATED APPLICATION(S)

This application is a Divisional of U.S. application Ser. No.10/756,901, filed Jan. 14, 2004, which is a Divisional of U.S.application Ser. No. 09/253,611 filed on Feb. 19, 1999, both of whichare incorporated herein by reference.

TECHNICAL FIELD

The invention relates generally to forming micro solder balls, and morespecifically to forming micro solder balls through selective depositionfor bonding integrated circuits to a module substrate or to a circuitboard.

BACKGROUND INFORMATION

The central processing units (CPUs) of most modern day computers aretypically provided on large circuit boards (mother boards) populatedwith various integrated circuit (IC) components, such as microprocessorsand memory devices. These components contain integrated circuits formedon semiconductor dies, generally for performing a specific function. Thecomponents work in conjunction with one another to perform the variousfunctions of the computer. Contacts on the mother board are connected tocontacts on the components by the use of multi-chip modules or directlyby conventional means, such as solder. The components are connected toone another by metal patterns formed on the surface of the module,mother board or other support. These metal patterns provide a conduitfor data exchange between the components.

There is a constant need for computers that operate at faster rates. Inorder to accommodate this need, various techniques have developed toincrease the rate (bandwidth) at which data can be processed andtransmitted. One of these involves increasing the circuit complexity ofthe integrated circuits which also often results in a larger package forthe semiconductor die, and an increase in the number of input/output(I/O) terminals required for the semiconductor die. Since the amount ofdata that can be accessed from or transferred to a component is directlyproportional to the number of I/O lines its semiconductor die contains,increasing the number of I/O terminals directly increases data transferand processing speed.

Traditionally, semiconductor dies were connected to leads with finewires (wire bonding). This method of connection was limited by thenumber of pads which could be placed on the periphery of thesemiconductor die. Considerable progress has been made in reducing thesemiconductor die pad size, thereby increasing the number of pads.However, this technology is still limited by the number of pads whichcan be formed on the die periphery, and therefore the number of I/Os ona die is likewise limited. Therefore, other techniques have beendeveloped over the years to increase the number of available I/Oterminals and while accommodating alignment problems.

One of these techniques, known as Controlled Collapse Chip Connection(C4), was developed in the 1960s to deal with the problems associatedwith alignment of semiconductor dies on a substrate. This process alsosought to increase the number of I/O terminals which could be madeavailable for each semiconductor die. The C4 process uses solder bumpsdeposited on flat contacts on the semiconductor dies to form the bondbetween the semiconductor die and the leads. The contacts and solderballs on the semiconductor dies are matched with similar flat contactson the leads to form the connection. Once the die is placed on top ofthe contacts, the entire device is heated to a temperature which meltsthe solder. As the solder is allowed to set, a reliable bond is formedbetween the chip and the leads.

One of the main advantages of this process is that the semiconductor dieself-aligns itself on the module substrate based on the high surfacetension of the solder. In other words, the chip need not be perfectlyaligned over the contacts of the substrate. As long as it is in closeproximity, the melting of the solder will align the chip with thesubstrate contacts. The other advantage of this process is that anincreased number of I/O terminals can be fabricated for eachsemiconductor die as bonding pads are not limited to the periphery ofthe die. This type of bonding process is also often referred to as“flip-chip” or “micro-bump” bonding. The process can be brieflyexplained with reference to FIGS. 1 and 2.

FIG. 1 shows a side view of a semiconductor die 10 and a support 20. Thesemiconductor die 10 is fabricated with various metal pattern lines andcontacts 50 imprinted on its last metal level, as shown in FIG. 2.Formed beneath the semiconductor die 10 is an array of solder balls 30.The support 20 includes metallized paths 60 for carrying signals fromthe semiconductor die 10 to other elements mounted on the support 20.These paths have contacts which match the contacts located on theunderside of the semiconductor die 10. When the semiconductor die 10 isready to be mounted, it is placed on top of the support 20 above thesupport contacts. The solder balls 30 attached to the contacts of thesemiconductor die rest on the contacts of the support, as shown inFIG. 1. When the device is heated, the solder melts and thesemiconductor die 10 self-aligns with the support contacts. The solderlater hardens to form a reliable bond between the two sets of contacts.FIG. 3 shows the device after the solder has been heated and set.

Traditionally, the contacts and solder balls have been formed on thesemiconductor die using metal mask technology. In this process, a metalmask (essentially a metal plate with a pattern of holes therein) isplaced over a substrate containing many semiconductor dies for formingthe contacts and solder balls. Then, contact material and solder areevaporated through the holes onto the wafer. The holes in the metalmasks must be of sufficient size to prevent warpage and damage of themask during use. Hence, the number of contacts that can be fabricatedthrough use of a metal mask is limited because the holes in the maskmust remain above a minimum size to prevent these problems.Consequently, the size of the solder balls that can be created issimilarly limited.

The minimum diameter of a C4 solder ball commonly achieved using currenttechniques, such as metal mask, is approximately 100 microns. Since thesize of the solder balls is directly related to the number and densityof I/O terminals that can be fabricated on a given semiconductor die, adecrease in solder ball size would provide for an increase in the numberand density of the I/O terminals. This would, in turn, allow for asignificant increase in data transmission rates because of the increasednumber of I/O ports for the packaged IC component.

Hence, there is currently a need for a process for forming solder ballcontacts which are less than 100 microns in diameter.

SUMMARY

The above-mentioned problems with I/O lines on a semiconductor die andother problems are addressed by the invention, and which will beunderstood by reading and studying the following specification.

One embodiment of the invention provides a method for forming solderball contacts using selective deposition of solder on metal contact padsof a device. The metal contact pads have exposed portions at the bottomof through holes. The through holes define the dimensions of the exposedportions of the metal contact pads, and serve to limit the dimensions ofthe resulting solder contact by limiting the area upon which depositionpreferentially occurs. Subsequent reflow of the deposited solder contactforms a solder ball contact. Solder ball contacts in accordance with theinvention are capable of attaining dimensions of approximately 2.5microns in diameter.

In one embodiment, the selective deposition includes immersion contactby immersing the device in molten solder. The molten solderpreferentially adheres to the exposed portions of the metal contact padsupon contact with the pads. Subsequent reflow of the deposited solderforms a solder ball contact.

In another embodiment, the selective deposition includes chemical vapordeposition of solder. Reactants capable of forming the solderpreferentially adhere to the exposed portions of the metal contact pads.The reactants react to form a solder contact on the exposed portions ofthe metal contact pads. Subsequent reflow of the deposited soldercontact forms a solder ball contact.

In a further embodiment, the selective deposition includes electrolyticdeposition of solder. The solder preferentially forms on the exposedportions of the metal contact pads placed in a cathodic state.Subsequent reflow of the deposited solder forms a solder ball contact.

In a still further embodiment, the selective deposition includeselectrolytic deposition of solder, where the solder is deposited usingmore than one layer of material. The layers of deposited materialforming the solder preferentially form on the exposed portions of themetal contact pads placed in a cathodic state. Subsequent reflow of thedeposited solder forms a solder ball contact.

Although particularly applicable for use as a replacement for thepresently-used processes of forming C4-type connections on semiconductordies, the same processes of the invention can also be used to formsolder ball connections on other supports or substrates.

The above and other advantages and features of the invention will bebetter understood from the following detailed description of variousembodiments of the invention which is provided in connection with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of an integrated circuit package before C4 bondsare created.

FIG. 2 is an elevation view of an integrated circuit package.

FIG. 3 is a plan view of an integrated circuit package after the C4bonds are created.

FIGS. 4(A)-4(P) are cross-sectional views of an integrated circuitstructure in accordance with one embodiment of the invention.

FIGS. 5(A)-5(C) are cross-sectional views of an integrated circuitstructure in accordance with another embodiment of the invention.

FIGS. 6(A)-6(C) are cross-sectional views of an integrated circuitstructure in accordance with still another embodiment of the invention.

FIG. 7 is a block diagram of an integrated circuit memory device inaccordance with an embodiment of the invention.

FIG. 8 is an elevation view of a wafer containing semiconductor dies inaccordance with an embodiment of the invention.

FIG. 9 is a block diagram of an exemplary circuit module in accordancewith an embodiment of the invention.

FIG. 10 is a block diagram of an exemplary memory module in accordancewith an embodiment of the invention.

FIG. 11 is a block diagram of an exemplary electronic system inaccordance with an embodiment of the invention.

FIG. 12 is a block diagram of an exemplary memory system in accordancewith an embodiment of the invention.

FIG. 13 is a block diagram of an exemplary computer system in accordancewith an embodiment of the invention.

DESCRIPTION OF THE EMBODIMENTS

In the following detailed description, reference is made to theaccompanying drawings which form a part hereof, and in which is shown byway of illustration specific embodiments in which the invention may bepracticed. These embodiments are described in sufficient detail toenable those skilled in the art to practice the invention, and it is tobe understood that other embodiments may be utilized and thatstructural, logical and electrical changes may be made without departingfrom the spirit and scope of the invention. The following detaileddescription is, therefore, not to be taken in a limiting sense, and thescope of the invention is defined by the appended claims. Like numbersin the figures refer to like components, which should be apparent fromthe context of use.

One embodiment of a process of the invention is explained below withreference to FIGS. 4(A)-4(P). Although the following explanation refersto a technique for placing solder ball contacts on a semiconductorwafer, those skilled in the art will recognize that the processdescribed below can be performed on a single semiconductor die. Further,it will also be apparent to those skilled in the art that the processdescribed below can be used to form solder balls on circuit boards orother support structures.

FIGS. 4(A)-4(P) illustrate the inventive process steps used to createmicro solder balls on a semiconductor wafer 110. FIG. 4(A) shows thefirst stage in the formation of the micro solder balls on the wafer 110. At this stage, an insulating layer 120, such as silicon dioxide(SiO₂), is deposited on the next to last layer of metallurgy 130 of thewafer 110 by a process such as chemical vapor deposition (CVD). The nextto last layer of metallurgy 130 includes the metal pattern lines thatare coupled to internal circuitry contained on the semiconductor wafer100. Although CVD silicon dioxide is preferred for the first insulatinglayer, other insulators (e.g., polyimide, silicon nitride, fluorinatedsilicon dioxide) known to those skilled in the art may also be used anddeposited by conventional techniques. The insulating layer 120 should beapplied so that its thickness is at least approximately 2 micronsgreater than the thickness of the next to last metal layer 130. Then,the structure 100 is planarized using a chemical mechanical polishingprocess (CMP). The resulting device, after polishing, is as shown inFIG. 4(B), where the excess insulating material has been smoothed away.

Next, as shown in FIG. 4(C), a first layer of photoresist 125 isdeposited over the insulating layer 120. This photoresist layer 125 maybe made of any type of photoresist known to those skilled in the art.The photoresist layer 125 is patterned, as shown in FIG. 4(D), to definefuture via holes. The patterned photoresist layer 125 is then used toetch into and remove portions of the insulating layer 120. FIG. 4(E)shows the device after the photoresist layer 125 has been exposed, thevia holes 140 have been etched, and the photoresist layer 125 has beenremoved. These via holes 140 provide a connection for upper conductivelevels to the next to last layer of metallurgy 130.

Next, solderable metal contact pads 150 are formed on the upper surfaceof the insulating layer 120. This is accomplished by depositing a secondphotoresist layer 145 on the planarized insulating layer 120, which willbe used as a liftoff layer.

FIG. 4(F) shows the device 100 after the photoresist layer 145 has beenplaced over the insulating layer 120. An insulator such as polyimide mayalso be used in place of the photoresist layer 145, but it has beenfound that photoresist provides the best results in the invention. Thisphotoresist layer 145 should be approximately 1.5 microns thick. Afterit is deposited, the photoresist layer 145 is patterned and etched downto the insulating layer 120 leaving exposed those areas on layer 120where the metal contact pads 150 are desired, as shown in FIG. 4(G).Then, a metal stack preferably containing Zirconium (Zr), Nickel (Ni),Copper (Cu), Gold (Au) and Lead (Pb) is formed overtop of the entiredevice 100 including over the remaining areas of photoresist layer 145and in the etched areas. This stack is formed by applying the fivedifferent metals, one at a time, and preferably in the order presented,using methods known in the art. The thicknesses of each layer of metalis preferably approximately 500 Angstroms of Zr, 750 Angstroms of Ni,5000 Angstroms of Cu, 750 Angstroms of Au and 500 Angstroms of Pb,although these thicknesses are not critical. These metal layers aredeposited to form metal stacks 150 in the etched areas of thephotoresist layer 145, and to form excess metal stacks 150′ on top ofthe photoresist layer 145. It will be recognized that other metallurgycan be utilized to form metal stacks 150 and 150′.

Since the photoresist layer 145 and the metal layers 150, 150′ areapplied over the entire surface of the device 100, it is necessary toremove the unwanted metal 150′ and photoresist 145 prior to the nextprocess step. FIG. 4(H) shows the device 100 after all metal layers havebeen deposited. The excess metal areas 150′ which lie overtop of thephotoresist layer 145, must now be removed. This is accomplished by aliftoff process. Liftoff processes are a well known method for removingunwanted portions of a device under fabrication. The present inventorhas found that a tape-assisted liftoff process is especially beneficialin the disclosed process. Tape liftoff processes, per se, are known inthe art, as evidenced by U.S. Pat. No. 5,240,878 to Fitzsimmons, whichis incorporated herein by reference. Tape liftoff processes arefrequently used to remove unwanted photoresist levels once an imagingand etching has taken place.

The tape utilized is an adhesive-backed polymer (not shown), which isapplied overtop of the entire metallized resist layer, so that itcontacts metal stacks 150′. The tape bonds to the metal stacks 150′,which are, in turn, bonded to the photoresist layer 145. The removal ofthe tape causes all of the metal stacks 150′ and photoresist 145 to bestripped away, leaving metal contact pads 150 in only those areas whichwere previously etched in the photoresist layer 145. The resultingdevice 100 after the tape liftoff appears as shown in FIG. 4(I).

After the metal contact pads 150 have been formed, a second insulatinglayer 160 is added overtop of the device 100, as shown in FIG. 4(J).This insulating layer 160 can be formed of conventional insulatingmaterial, such as polyimide, and is preferably approximately 1.5 micronsthick. Although polyimide is preferred for this layer, any insulatorknown to those skilled in the art may be used (e.g., silicon dioxide,silicon nitride, fluorinated silicon dioxide).

FIG. 4(K) shows the next step where a third photoresist layer 170 isdeposited. The photoresist layer 170 is preferably approximately 2.5microns thick. The photoresist layer 170 is exposed and patterned, asshown in FIG. 4(L), to define through holes 180 in the areas above themetal contact pads 150. Then, the insulator 160 is etched through theholes 180 so that portions of the metal contact pads 150 are exposed, asshown in FIG. 4(M).

Next, as shown in FIG. 4(N), the photoresist layer 170 is removed fromdevice 100. In one embodiment, solder is selectively deposited on theexposed portions of metal contact pads 150, forming solder contacts 200in the through holes 180, by immersing the device 100 in molten solder.The molten solder will selectively attach to the exposed metal uponcontact, forming solder contacts 200 shown in FIG. 4(0).

Solder contacts 200 which connect with metal contact pads 150 projectout of the top surface of insulating layer 160. In a further step, thesolder contacts 200 may be heated, preferably in a H₂ ambient, to allowthem to reflow. When the solder contacts 200 are reflowed they reshapeto form solder ball contacts 210, approximating a spherical shape asshown in FIG. 4(P) due to minimization of stress, and the surfacetension of the molten solder. The solder may be a lead-tin solder(PbSn), bismuth solders or other solders known in the art.

Another embodiment is also described with reference to FIGS. 4(A)-4(P).In this embodiment, after the removing the photoresist layer 170 asshown in FIG. 4(N), solder is selectively deposited on the exposedportions of metal contact pads 150, forming solder contacts 200 in thethrough holes 180. The solder is selectively deposited on device 100using selective chemical vapor deposition (CVD). CVD utilizes reactivegaseous or vaporized components, i.e., reactants, which combine to forma desired species and, often, a gaseous by-product. The reactants arefed into a reaction chamber such that the reactants contact a substrateon which deposition is to occur. The mechanism generally involves thereactants being adsorbed on the substrate surface, where they undergo afilm-forming chemical reaction thus forming a film on the substratesurface. The film contains the desired species, and by-products aregenerally removed from a reaction chamber through venting or purging. Inthis embodiment, the reactants for a metal species should preferentiallybe adsorbed on the exposed portions of the metal contact pads 150.Subsequent reaction of reactants adsorbed on the exposed portions of themetal contact pads 150 form solder contacts 200 shown in FIG. 4(O).

As with the previous embodiment, solder contacts 200 which connect withmetal contact pads 150 project out of the top surface of insulatinglayer 160. In a further step, the solder contacts 200 may be heated,preferably in a H₂ ambient, to allow them to reflow. When the soldercontacts 200 are reflowed they reshape to form solder ball contacts 210,approximating a spherical shape as shown in FIG. 4(P) due tominimization of stress, and the surface tension of the molten solder.

A further embodiment is described with reference to FIGS. 4(A)-4(M) and5(A)-5(C). In this embodiment, processing proceeds to the etching ofthrough holes 180 to metal contact pads 150 as shown in FIG. 4(M).Instead of removing the resist at this stage, as in the previousembodiments, solder is applied to the exposed portions of metal contactpads 150 through electrolysis, or electrolytic deposition. Electrolyticdeposition generally utilizes a conductive solution of a solvent and anionically dissociated solute. Through the application of electricalcurrent, metal is deposited at a cathode from a solution containingmetal ions. By contacting the exposed portions of the metal contact pads150 with a conductive solution containing metal ions and placing themetal contact pads 150 in a cathodic state, i.e., making them negativeelectrodes, solder is selectively deposited on metal contact pads 150 ascurrent is passed through the conductive solution. The deposited solderforms solder contacts 200 as shown in FIG. 5(A). Solder contacts 200 arepreferably about 2.33 microns deep.

Photoresist layer 170 is then removed, exposing solder contacts 200above the surface of insulating layer 160 as shown in FIG. 5(B). In afurther step, the solder contacts 200 may be heated, preferably in a H₂ambient, to allow them to reflow. When the solder contacts 200 arereflowed they may reshape to form solder ball contacts 210,approximating a spherical shape similar to those shown in FIG. 4(P) dueto minimization of stress, and the surface tension of the molten solder.Alternatively, by limiting the annealing conditions, i.e., time andtemperature, such that the solder contacts 200 are not fully molten,solder ball contacts 210 may be composite contacts, including both aflat contact portion 215 and a spherical portion 220 in a single unit asshown in FIG. 5(C).

A still further embodiment is described with reference to FIGS.4(A)-4(M) and 6(A)-6(C). In this embodiment, processing proceeds to theetching of through holes 180 to metal contact pads 150 as shown in FIG.4(M). Instead of removing the resist at this stage, a layer of lead 225is applied to the exposed portions of metal contact pads 150 throughelectrolysis. A layer of tin 230 is then formed on the layer of lead225. The lead layer 225 is preferably approximately 0.91 microns deep.The tin layer 230 is preferably approximately 1.42 microns deep. Thelead layer 225 and the tin layer 230 collectively form the soldercontacts 200 as shown in FIG. 6(A). Other metallurgies may besubstituted for the lead/tin combination, and the deposition may includemore than two layers.

Photoresist layer 170 is then removed, exposing solder contacts 200above the surface of insulating layer 160 as shown in FIG. 6(B). In afurther step, the solder contacts 200 may be heated, preferably in a H₂ambient, to allow them to reflow. When the solder contacts 200 arereflowed they may reshape to form solder ball contacts 210,approximating a spherical shape similar to those shown in FIG. 4(P) dueto minimization of stress, and the surface tension of the molten solder.Alternatively, by limiting the annealing conditions, i.e., time andtemperature, such that the solder contacts 200 are not fully molten,solder ball contacts 210 may be composite contacts, including both aflat contact portion 215 and a spherical portion 220 in a single unit asshown in FIG. 6(C).

Because these solder ball contacts of the invention are formed byselective deposition of solder using fine closely spaced holes, the sizeof the contacts is decreased significantly. Solder contacts formed inaccordance with the invention are capable of attaining dimensions ofapproximately 2.5 microns in diameter, using a hole of approximately 2microns in diameter. This is a significant improvement over the priorart solder ball contacts previously described, which are currently onthe order of 100 microns in diameter.

Although the invention can be used to form solder ball contacts whichare approximately 2.5 microns in diameter, it can also be used by thoseskilled in the art to produce solder contacts of other sizes, butparticularly those in the range of 2.5 microns to 100 microns. Forexample, it might be desirable to form solder contacts of 10, 25, 50 or75 microns, or any other size in the range of 2.5 to 100 microns, or ina narrower range such as less than 50 microns, or less than 25 microns,or less than 10 microns, as non-limiting examples.

Memory Devices

FIG. 7 is a simplified block diagram of a memory device according to oneembodiment of the invention. The memory device 300 includes an array ofmemory cells 302, address decoder 304, row access circuitry 306, columnaccess circuitry 308, control circuitry 310, and Input/Output circuit312. The memory can be coupled to an external microprocessor 314, ormemory controller for memory accessing. The memory receives controlsignals from the processor 314, such as WE*, RAS* and CAS* signals. Thememory is used to store data which is accessed via I/O lines. It will beappreciated by those skilled in the art that additional circuitry andcontrol signals can be provided, and that the memory device of FIG. 7has been simplified to help focus on the invention. Thus, the memoryincludes internal circuitry, metal pattern lines coupled to the array ofmemory cells and internal circuitry, and metal contact pads coupled tothe metal pattern lines. At least one of the metal contact pads iscoupled to a solder ball contact of the invention.

It will be understood that the above description of a DRAM (DynamicRandom Access Memory) is intended to provide a general understanding ofthe memory and is not a complete description of all the elements andfeatures of a DRAM. Further, the invention is equally applicable to anysize and type of memory circuit and is not intended to be limited to theDRAM described above. Other alternative types of devices include SRAM(Static Random Access Memory) or Flash memories. Additionally, the DRAMcould be a synchronous DRAM commonly referred to as SGRAM (SynchronousGraphics Random Access Memory), SDRAM (Synchronous Dynamic Random AccessMemory), SDRAM II, and DDR SDRAM (Double Data Rate SDRAM), as well asSynchlink or Rambus DRAMs.

As recognized by those skilled in the art, memory devices of the typedescribed herein are generally fabricated as an integrated circuitcontaining a variety of semiconductor devices. The integrated circuit issupported by a substrate. A substrate is often a silicon wafer, but canadditionally refer to silicon-on-insulator (SOI) technology,silicon-on-sapphire (SOS) technology, thin film transistor (TFT)technology and other applicable support structures. The integratedcircuits are typically repeated multiple times on each substrate. Thesubstrate is further processed to separate the integrated circuits intodies as is well known in the art.

Semiconductor Dies

With reference to FIG. 8, in one embodiment, a semiconductor die 710 isproduced from a silicon wafer 700. A die is an individual pattern,typically rectangular, on a substrate that contains circuitry, orintegrated circuit devices, to perform a specific function. Theintegrated circuit devices of semiconductor die 710 are coupled to metalpattern lines. The metal pattern lines are coupled to metal contactpads. At least one of the metal contact pads is coupled to a solder ballcontact as disclosed herein. A semiconductor wafer will typicallycontain a repeated pattern of such dies containing the samefunctionality. Die 710 may contain circuitry for the inventive memorydevice, as discussed above. Die 710 may further contain additionalcircuitry to extend to such complex devices as a monolithic processorwith multiple functionality. Die 710 is typically packaged in aprotective casing (not shown) with leads extending therefrom (not shown)providing access to the circuitry of the die for unilateral or bilateralcommunication and control.

Circuit Modules

As shown in FIG. 9, two or more dies 710 may be combined, with orwithout protective casing, into a circuit module 800 to enhance orextend the functionality of an individual die 710. Circuit module 800may be a combination of dies 710 representing a variety of functions, ora combination of dies 710 containing the same functionality. Someexamples of a circuit module include memory modules, device drivers,power modules, communication modems, processor modules andapplication-specific modules and may include multilayer, multichipmodules. Circuit module 800 may be a subcomponent of a variety ofelectronic systems, such as a clock, a television, a cell phone, apersonal computer, an automobile, an industrial control system, anaircraft and others. Circuit module 800 will have a variety of leads 810extending therefrom and coupled to the dies 710 providing unilateral orbilateral communication and control.

FIG. 10 shows one embodiment of a circuit module as memory module 900.Memory module 900 generally depicts a Single Inline Memory Module (SIMM)or Dual Inline Memory Module (DIMM). A SIMM or DIMM is generally aprinted circuit board (PCB) or other support containing a series ofmemory devices. While a SIMM will have a single in-line set of contactsor leads, a DIMM will have a set of leads on each side of the supportwith each set representing separate I/O signals. Memory module 900contains multiple memory devices 910 contained on support 915, thenumber depending upon the desired bus width and the desire for parity.Memory module 900 may contain memory devices 910 on both sides ofsupport 915. Memory module 900 accepts a command signal from an externalcontroller (not shown) on a command link 920 and provides for data inputand data output on data links 930. The command link 920 and data links930 are connected to leads 940 extending from the support 915. Leads 940are shown for conceptual purposes and are not limited to the positionsshown in FIG. 10.

Electronic Systems

FIG. 11 shows an electronic system 1000 containing one or more circuitmodules 800. Electronic system 1000 generally contains a user interface1010. User interface 1010 provides a user of the electronic system 1000with some form of control or observation of the results of theelectronic system 1000. Some examples of user interface 1010 include thekeyboard, pointing device, monitor and printer of a personal computer;the tuning dial, display and speakers of a radio; the ignition switchand gas pedal of an automobile; and the card reader, keypad, display andcurrency dispenser of an automated teller machine. User interface 1010may further describe access ports provided to electronic system 1000.Access ports are used to connect an electronic system to the moretangible user interface components previously exemplified. One or moreof the circuit modules 800 may be a processor providing some form ofmanipulation, control or direction of inputs from or outputs to userinterface 1010, or of other information either preprogrammed into, orotherwise provided to, electronic system 1000. As will be apparent fromthe lists of examples previously given, electronic system 1000 willoften contain certain mechanical components (not shown) in addition tocircuit modules 800 and user interface 1010. It will be appreciated thatthe one or more circuit modules 800 in electronic system 1000 can bereplaced by a single integrated circuit. Furthermore, electronic system1000 may be a subcomponent of a larger electronic system.

FIG. 12 shows one embodiment of an electronic system as memory system1100. Memory system 1100 contains one or more memory modules 900 and amemory controller 1110. Memory controller 1110 provides and controls abidirectional interface between memory system 1100 and an externalsystem bus 1120. Memory system 1100 accepts a command signal from theexternal bus 1120 and relays it to the one or more memory modules 900 ona command link 1130. Memory system 1100 provides for data input and dataoutput between the one or more memory modules 900 and external systembus 1120 on data links 1140.

FIG. 13 shows a further embodiment of an electronic system as a computersystem 1200. Computer system 1200 contains a processor 1210 and a memorysystem 1100 housed in a computer unit 1205. Computer system 1200 is butone example of an electronic system containing another electronicsystem, i.e., memory system 1100, as a subcomponent. Computer system1200 optionally contains user interface components. Depicted in FIG. 13are a keyboard 1220, a pointing device 1230, a monitor 1240, a printer1250 and a bulk storage device 1260. It will be appreciated that othercomponents are often associated with computer system 1200 such asmodems, device driver cards, additional storage devices, etc. It willfurther be appreciated that the processor 1210 and memory system 1100 ofcomputer system 1200 can be incorporated on a single integrated circuit.Such single package processing units reduce the communication timebetween the processor and the memory circuit.

Conclusion

Methods of forming solder ball contacts having dimensions ofapproximately 2.5 microns in diameter have been described. Variousdevices, modules, systems and other apparatus utilizing the solder ballcontacts of the invention have been further described. Apparatusutilizing the solder ball contacts of the invention are capable ofincreased I/O density over conventional C4 technologies.

While the invention has been described and illustrated with respect toforming solder ball contacts on a semiconductor die, it should beapparent that the same processing techniques can be used to form solderball contacts on a support, a printed circuit board or otherconductor-bearing substrate.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement which is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. Many adaptations ofthe invention will be apparent to those of ordinary skill in the art.For example, other methods of producing the metal contact pads andthrough holes may be used without departing from the scope of theinvention. In addition, other metallurgies may be used for the solder orthe metal contact pads. Accordingly, this application is intended tocover any adaptations or variations of the invention. It is manifestlyintended that this invention be limited only by the following claims andequivalents thereof.

1. A semiconductor die comprising: an integrated circuit supported by asubstrate; a metal pattern line coupled to the integrated circuit; ametal contact pad coupled to the metal pattern line; and a solder ballcontact coupled to the metal contact pad, wherein the solder ballcontact is formed by a method, the method including: forming aninsulating layer on the metal contact pad; removing a portion of theinsulating layer to expose a portion of the metal contact pad, therebyforming an exposed portion of the metal contact pad; depositing solderon the exposed portion of the metal contact pad using a selectivedeposition, thereby forming a solder contact; and annealing the soldercontact to form the solder ball contact.
 2. The semiconductor die ofclaim 1, wherein the selective deposition includes immersion contact. 3.The semiconductor die of claim 1, wherein the selective depositionincludes electrolytic deposition.
 4. The semiconductor die of claim 1,wherein the selective deposition includes chemical vapor deposition. 5.The semiconductor die of claim 1, wherein the solder includes at leastone material selected from the group consisting of lead, tin andbismuth.
 6. The semiconductor die of claim 1, wherein the metal contactpad includes a stack of zirconium, nickel, copper, gold, and lead. 7.The semiconductor die of claim 1, wherein the exposed portion of themetal contact pad has a diameter, wherein the diameter has a dimensionranging from a first dimension to a second dimension greater than thefirst dimension, and wherein the first dimension is approximately 2microns.
 8. A semiconductor die comprising: an integrated circuitsupported by a substrate; a metal pattern line coupled to the integratedcircuit; a metal contact pad coupled to the metal pattern line; and asolder ball contact coupled to the metal contact pad, wherein the solderball contact is formed by a method, the method including: depositing aninsulating layer on the metal contact pad; removing a portion of theinsulating layer to expose a portion of the metal contact pad, therebyforming an exposed portion of the metal contact pad; immersing thesubstrate in molten solder to form a solder contact on the exposedportion of the metal contact pad; and annealing the solder contact toform the solder ball contact.
 9. The semiconductor die of claim 8,wherein the molten solder includes at least one material selected fromthe group consisting of lead, tin and bismuth.
 10. A semiconductor diecomprising: an integrated circuit supported by a substrate; a metalpattern line coupled to the integrated circuit; a metal contact padcoupled to the metal pattern line; and a solder ball contact coupled tothe metal contact pad, wherein the solder ball contact is formed by amethod, the method including: forming an insulating layer on the metalcontact pad; removing a portion of the insulating layer to expose aportion of the metal contact pad, thereby forming an exposed portion ofthe metal contact pad; adsorbing reactants on the exposed portion of themetal contact pad; reacting the reactants on the exposed portion of themetal contact pad, thereby forming a solder contact; and annealing thesolder contact to form the solder ball contact.
 11. A semiconductor diecomprising: an integrated circuit supported by a substrate; a metalpattern line coupled to the integrated circuit; a metal contact padcoupled to the metal pattern line; and a solder ball contact coupled tothe metal contact pad, wherein the solder ball contact is formed by amethod, the method including: forming an insulating layer on the metalcontact pad; forming a resist layer on the insulating layer; patterningthe resist layer to define a future exposed portion of the metal contactpad; removing a portion of the insulating layer to expose a portion ofthe metal contact pad, thereby forming the exposed portion of the metalcontact pad; electrolytically depositing solder on the exposed portionof the metal contact pad, thereby forming a solder contact; removing theresist layer, thereby exposing the solder contact above a surface of theinsulating layer; and annealing the solder contact to form the solderball contact.
 12. The semiconductor die of claim 1 1, wherein the soldercomprises at least one material selected from the group consisting oflead, tin and bismuth.
 13. An electronic system, comprising: aprocessor; and a circuit module having a plurality of leads coupled tothe processor, and further having a semiconductor die coupled to theplurality of leads, wherein the semiconductor die comprises: anintegrated circuit supported by a substrate; a metal pattern linecoupled to the integrated circuit; a metal contact pad coupled to themetal pattern line; and a solder ball contact coupled to the metalcontact pad, wherein the solder ball contact is formed by a method, themethod including: forming an insulating layer on the metal contact pad;removing a portion of the insulating layer to expose a portion of themetal contact pad, thereby forming an exposed portion of the metalcontact pad; depositing solder on the exposed portion of the metalcontact pad using a selective deposition, thereby forming a soldercontact; and annealing the solder contact to form the solder ballcontact.
 14. The electronic system of claim 13, wherein the selectivedeposition includes immersion contact.
 15. The electronic system ofclaim 13, wherein the selective deposition includes electrolyticdeposition.
 16. The electronic system of claim 13, wherein the selectivedeposition includes chemical vapor deposition.
 17. The electronic systemof claim 13, wherein the solder includes at least one material selectedfrom the group consisting of lead, tin and bismuth.
 18. The electronicsystem of claim 13, wherein the metal contact pad includes a stack ofzirconium, nickel, copper, gold, and lead.
 19. The electronic system ofclaim 13, wherein the exposed portion of the metal contact pad has adiameter, wherein the diameter has a dimension ranging from a firstdimension to a second dimension greater than the first dimension, andwherein the first dimension is approximately 2 microns.
 20. Anelectronic system, comprising: a processor; and a circuit module havinga plurality of leads coupled to the processor, and further having asemiconductor die coupled to the plurality of leads, wherein thesemiconductor die comprises: an integrated circuit supported by asubstrate; a metal pattern line coupled to the integrated circuit; ametal contact pad coupled to the metal pattern line; and a solder ballcontact coupled to the metal contact pad, wherein the solder ballcontact is formed by a method, the method including: depositing aninsulating layer on the metal contact pad; removing a portion of theinsulating layer to expose a portion of the metal contact pad, therebyforming an exposed portion of the metal contact pad; immersing thesubstrate in molten solder to form a solder contact on the exposedportion of the metal contact pad; and annealing the solder contact toform the solder ball contact.
 21. The electronic system of claim 20,wherein the molten solder comprises at least one material selected fromthe group consisting of lead, tin and bismuth.
 22. An electronic system,comprising: a processor; and a circuit module having a plurality ofleads coupled to the processor, and further having a semiconductor diecoupled to the plurality of leads, wherein the semiconductor diecomprises: an integrated circuit supported by a substrate; a metalpattern line coupled to the integrated circuit; a metal contact padcoupled to the metal pattern line; and a solder ball contact coupled tothe metal contact pad, wherein the solder ball contact is formed by amethod, the method including: forming an insulating layer on the metalcontact pad; removing a portion of the insulating layer to expose aportion of the metal contact pad, thereby forming an exposed portion ofthe metal contact pad; adsorbing reactants on the exposed portion of themetal contact pad; reacting the reactants on the exposed portion of themetal contact pad, thereby forming a solder contact; and annealing thesolder contact to form the solder ball contact.
 23. An electronicsystem, comprising: a processor; and a circuit module having a pluralityof leads coupled to the processor, and further having a semiconductordie coupled to the plurality of leads, wherein the semiconductor diecomprises: an integrated circuit supported by a substrate; a metalpattern line coupled to the integrated circuit; a metal contact padcoupled to the metal pattern line; and a solder ball contact coupled tothe metal contact pad, wherein the solder ball contact is formed by amethod, the method including: forming an insulating layer on the metalcontact pad; forming a resist layer on the insulating layer; patterningthe resist layer to define a future exposed portion of the metal contactpad; removing a portion of the insulating layer to expose a portion ofthe metal contact pad, thereby forming the exposed portion of the metalcontact pad; electrolytically depositing solder on the exposed portionof the metal contact pad, thereby forming a solder contact; removing theresist layer, thereby exposing the solder contact above a surface of theinsulating layer; and annealing the solder contact to form the solderball contact.
 24. The electronic system of claim 23, wherein the soldercomprises at least one material selected from the group consisting oflead, tin and bismuth.
 25. A memory module comprising: a support; aplurality of leads extending from the support; a command link coupled toat least one of the plurality of leads; a plurality of data links,wherein each data link is coupled to at least one of the plurality ofleads; and at least one memory device contained on the support andcoupled to the command link, wherein the at least one memory devicecomprises: an integrated circuit supported by a substrate; a metalpattern line coupled to the integrated circuit; a metal contact padcoupled to the metal pattern line; and a solder ball contact coupled tothe metal contact pad, wherein the solder ball contact is formed by amethod, the method including: forming an insulating layer on the metalcontact pad; removing a portion of the insulating layer to expose aportion of the metal contact pad, thereby forming an exposed portion ofthe metal contact pad; depositing solder on the exposed portion of themetal contact pad using a selective deposition, thereby forming a soldercontact; and annealing the solder contact to form the solder ballcontact.
 26. The memory module of claim 25, wherein the selectivedeposition includes immersion contact.
 27. The memory module of claim25, wherein the selective deposition includes electrolytic deposition.28. The memory module of claim 25, wherein the selective depositionincludes chemical vapor deposition.
 29. The memory module of claim 25,wherein the solder includes at least one material selected from thegroup consisting of lead, tin and bismuth.
 30. The memory module ofclaim 25, wherein the metal contact pad includes a stack of zirconium,nickel, copper, gold, and lead.
 31. The memory module of claim 25,wherein the exposed portion of the metal contact pad has a diameter,wherein the diameter has a dimension ranging from a first dimension to asecond dimension greater than the first dimension, and wherein the firstdimension is approximately 2 microns.
 32. A memory module comprising: asupport; a plurality of leads extending from the support; a command linkcoupled to at least one of the plurality of leads; a plurality of datalinks, wherein each data link is coupled to at least one of theplurality of leads; and at least one memory device contained on thesupport and coupled to the command link, wherein the at least one memorydevice comprises: an integrated circuit supported by a substrate; ametal pattern line coupled to the integrated circuit; a metal contactpad coupled to the metal pattern line; and a solder ball contact coupledto the metal contact pad, wherein the solder ball contact is formed by amethod, the method including: depositing an insulating layer on themetal contact pad; removing a portion of the insulating layer to exposea portion of the metal contact pad, thereby forming an exposed portionof the metal contact pad; immersing the substrate in molten solder toform a solder contact on the exposed portion of the metal contact pad;and annealing the solder contact to form the solder ball contact. 33.The memory module of claim 32, wherein the molten solder comprises atleast one material selected from the group consisting of lead, tin andbismuth.
 34. A memory module comprising: a support; a plurality of leadsextending from the support; a command link coupled to at least one ofthe plurality of leads; a plurality of data links, wherein each datalink is coupled to at least one of the plurality of leads; and at leastone memory device contained on the support and coupled to the commandlink, wherein the at least one memory device comprises: an integratedcircuit supported by a substrate; a metal pattern line coupled to theintegrated circuit; a metal contact pad coupled to the metal patternline; and a solder ball contact coupled to the metal contact pad,wherein the solder ball contact is formed by a method, the methodincluding: forming an insulating layer on the metal contact pad;removing a portion of the insulating layer to expose a portion of themetal contact pad, thereby forming an exposed portion of the metalcontact pad; adsorbing reactants on the exposed portion of the metalcontact pad; reacting the reactants on the exposed portion of the metalcontact pad, thereby forming a solder contact; and annealing the soldercontact to form the solder ball contact.
 35. A memory module comprising:a support; a plurality of leads extending from the support; a commandlink coupled to at least one of the plurality of leads; a plurality ofdata links, wherein each data link is coupled to at least one of theplurality of leads; and at least one memory device contained on thesupport and coupled to the command link, wherein the at least one memorydevice comprises: an integrated circuit supported by a substrate; ametal pattern line coupled to the integrated circuit; a metal contactpad coupled to the metal pattern line; and a solder ball contact coupledto the metal contact pad, wherein the solder ball contact is formed by amethod, the method including: forming an insulating layer on the metalcontact pad; forming a resist layer on the insulating layer; patterningthe resist layer to define a future exposed portion of the metal contactpad; removing a portion of the insulating layer to expose a portion ofthe metal contact pad, thereby forming the exposed portion of the metalcontact pad; electrolytically depositing solder on the exposed portionof the metal contact pad, thereby forming a solder contact; removing theresist layer, thereby exposing the solder contact above a surface of theinsulating layer; and annealing the solder contact to form the solderball contact.
 36. The memory module of claim 35, wherein the soldercomprises at least one material selected from the group consisting oflead, tin and bismuth.
 37. A memory system comprising: a controller; acommand link coupled to the controller; a data link coupled to thecontroller; and a memory device coupled to the command link and the datalink, wherein the memory device comprises: an integrated circuitsupported by a substrate; a metal pattern line coupled to the integratedcircuit; a metal contact pad coupled to the metal pattern line; and asolder ball contact coupled to the metal contact pad, wherein the solderball contact is formed by a method, the method including: forming aninsulating layer on the metal contact pad; removing a portion of theinsulating layer to expose a portion of the metal contact pad, therebyforming an exposed portion of the metal contact pad; depositing solderon the exposed portion of the metal contact pad using a selectivedeposition, thereby forming a solder contact; and annealing the soldercontact to form the solder ball contact.
 38. The memory system of claim37, wherein the selective deposition includes immersion contact.
 39. Thememory system of claim 37, wherein the selective deposition includeselectrolytic deposition.
 40. The memory system of claim 37, wherein theselective deposition includes chemical vapor deposition.
 41. The memorysystem of claim 37, wherein the solder includes at least one materialselected from the group consisting of lead, tin and bismuth.
 42. Thememory system of claim 37, wherein the metal contact pad includes astack of zirconium, nickel, copper, gold, and lead.
 43. The memorysystem of claim 37, wherein the exposed portion of the metal contact padhas a diameter, wherein the diameter has a dimension ranging from afirst dimension to a second dimension greater than the first dimension,and wherein the first dimension is approximately 2 microns.
 44. A memorysystem comprising: a controller; a command link coupled to thecontroller; a data link coupled to the controller; and a memory devicecoupled to the command link and the data link, wherein the memory devicecomprises: an integrated circuit supported by a substrate; a metalpattern line coupled to the integrated circuit; a metal contact padcoupled to the metal pattern line; and a solder ball contact coupled tothe metal contact pad, wherein the solder ball contact is formed by amethod, the method including: depositing an insulating layer on themetal contact pad; removing a portion of the insulating layer to exposea portion of the metal contact pad, thereby forming an exposed portionof the metal contact pad; immersing the substrate in molten solder toform a solder contact on the exposed portion of the metal contact pad;and annealing the solder contact to form the solder ball contact. 45.The memory system of claim 44, wherein the molten solder comprises atleast one material selected from the group consisting of lead, tin andbismuth.
 46. A memory system comprising: a controller; a command linkcoupled to the controller; a data link coupled to the controller; and amemory device coupled to the command link and the data link, wherein thememory device comprises: an integrated circuit supported by a substrate;a metal pattern line coupled to the integrated circuit; a metal contactpad coupled to the metal pattern line; and a solder ball contact coupledto the metal contact pad, wherein the solder ball contact is formed by amethod, the method including: forming an insulating layer on the metalcontact pad; removing a portion of the insulating layer to expose aportion of the metal contact pad, thereby forming an exposed portion ofthe metal contact pad; adsorbing reactants on the exposed portion of themetal contact pad; reacting the reactants on the exposed portion of themetal contact pad, thereby forming a solder contact; and annealing thesolder contact to form the solder ball contact.
 47. A memory systemcomprising: a controller; a command link coupled to the controller; adata link coupled to the controller; and a memory device coupled to thecommand link and the data link, wherein the memory device comprises: anintegrated circuit supported by a substrate; a metal pattern linecoupled to the integrated circuit; a metal contact pad coupled to themetal pattern line; and a solder ball contact coupled to the metalcontact pad, wherein the solder ball contact is formed by a method, themethod including: forming an insulating layer on the metal contact pad;forming a resist layer on the insulating layer; patterning the resistlayer to define a future exposed portion of the metal contact pad;removing a portion of the insulating layer to expose a portion of themetal contact pad, thereby forming the exposed portion of the metalcontact pad; electrolytically depositing solder on the exposed portionof the metal contact pad, thereby forming a solder contact; removing theresist layer, thereby exposing the solder contact above a surface of theinsulating layer; and annealing the solder contact to form the solderball contact.
 48. The memory system of claim 47, wherein the soldercomprises at least one material selected from the group consisting oflead, tin and bismuth.
 49. A semiconductor die comprising: an integratedcircuit supported by a substrate; a metal pattern line coupled to theintegrated circuit; a metal contact pad coupled to the metal patternline; and a solder ball contact coupled to the metal contact pad,wherein the solder ball contact is formed by a method, the methodincluding: forming an insulating layer on the metal contact pad; forminga patterned resist layer over the insulating layer; using the patternedresist layer as a mask to remove a portion of the insulating layer toexpose a portion of the metal contact pad, thereby forming an exposedportion of the metal contact pad; depositing solder on the exposedportion of the metal contact pad after the patterned resist layer isremoved, thereby forming a solder contact; and annealing the soldercontact to form the solder ball contact.
 50. The semiconductor die ofclaim 49, wherein depositing solder on the exposed portion of the metalcontact pad uses a deposition process selected from a group consistingof selective chemical vapor deposition and selective electrolyticdeposition.
 51. The semiconductor die of claim 49, wherein depositingsolder on the exposed portion of the metal contact pad includesdepositing solder only on the exposed portion of the metal contactwithout depositing solder on the insulating layer and without removing aremaining portion of the insulating layer.
 52. The semiconductor die ofclaim 49, wherein a remaining portion of the insulating layer remains inthe semiconductor die after the resist layer is removed.
 53. Thesemiconductor die of claim 49, wherein the solder includes at least onematerial selected from the group consisting of lead, tin and bismuth.54. The semiconductor die of claim 49, wherein the metal contact padincludes a stack of zirconium, nickel, copper, gold, and lead.
 55. Thesemiconductor die of claim 49, wherein the exposed portion of the metalcontact pad has a diameter, wherein the diameter has a dimension rangingfrom a first dimension to a second dimension greater than the firstdimension, and wherein the first dimension is approximately 2 microns.